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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 5046017 B1

PDFFull Text
Date of Patent:
Sep. 03, 1991

Filed:

Dec. 21, 1988

Wiring design for semiconductor integrated circuit

Applicant:
Inventors:

Kyoji Yuyama, Shiroyama, JP;

Kouichi Nishizawa, Aizuwakamatsu, JP;

Assignees:

Hitachi, Ltd., Tokyo, JP;

Hitachi Microcomputer Engineering, Ltd., Tokyo, JP;

Attorney:

Antonelli, Terry, Stout & Kraus

Primary Examiner:

Parshotam S Lall

Assistant Examiner:

V N Trans

Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 364490 ; 364489 ; 364488 ;
Abstract

A method of designing semiconductor integrated circuits wherein rough routes are designated after a process of design for cells layout is completed, then wirings between cells are supposed automatically on the basis of the designated rough routes, investigation of the characteristic of the wirings is executed, and after a target characteristic is attained, a wiring pattern satisfying all of required electrical and physical conditions, including layout rules, i.e. a detailed wiring pattern, is prepared.

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Yuyama, Kyoji. (1991). Wiring design for semiconductor integrated circuit (U.S. Patent No. 5046017). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5046017

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