Multiprocessor cache memory housekeeping

Abstract

Each housekeeping command calls for a corresponding combination of write back and flag reset operations. In laundering, a write back operation is performed for owner entries in a specified address set without invalidating those entries. In flushing, a launder is followed by a flag reset invalidating the entries in the address set. Also, the command indicates which of the valid flags should be reset. In demapping, only the flags making an entry inaccessible to the cache's processor are reset. The entries in the address set are selected based on two numbers which together provide a base three number. Each base three digit of this number specifies whether the corresponding real address bit of the entry will match if it is one or zero or 'don't care'. This permits housekeeping on any consecutive range of N addresses by specifying no more than 2 log.sub.2 N address sets which exactly cover that range. A processor initiates housekeeping by causing its cache to send a command indicating the operations to be performed and the numbers selecting the address set. In response, all caches pull down a line indicating housekeeping in progress, and that line remains down until the last cache has completed housekeeping, at which time the initiating processor is freed. Meanwhile, however, each of the caches interrupts housekeeping if it receives a command, so that non-housekeeping functions are not delayed by housekeeping. For this purpose, the execution of a housekeeping command is divided into incremental write back and flag reset operations after each of which the cache tests whether it has received a command. If not, housekeeping continues with the next write back or flag reset operation.