The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 1991

Filed:

Dec. 20, 1988
Applicant:
Inventors:

Yutaka Kobayashi, Katsuta-shi, Ibaraki-ken, JP;

Akihiro Tanba, Hitachi-shi, Ibaraki-ken, JP;

Ryoichi Hori, Nishitama-gun, Tokyo, JP;

Kyoichiro Asayama, Tachikawa-shi, Tokyo, JP;

Seigoh Yukutake, Hitachi-shi, Ibaraki-ken, JP;

Hiroyuki Miyazawa, Kodaira-shi, Tokyo, JP;

Kazumasa Yanagisawa, Kokubunji-shi, Tokyo, JP;

Goro Kitsukawa, Nishitama-gun, Tokyo, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 236 ; 357 43 ; 357 47 ; 357 50 ; 357 54 ;
Abstract

A small and reliable semiconductor device is provided in a substrate which has an isolation trench and a capacitor trench. The isolation trench isolates a bipolar transistor from other semiconductor devices, and the capacitor trench provides capacitance to a memory cell which is formed in the substrate. The interior of the device isolation trench is kept in a floating state with respect to the surrounding semiconductor regions by forming an insulating film over the inner surface of the trench. In the capacitor trench, insulating layers and resilient conductive layers are formed alternately to form capacitance between the opposing conductive layers.


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