Low power programming circuit for user programmable digital logic array

Abstract

A programming circuit for an array of bipolar transistors which is selectable by row and column decoders to form a selected logic circuit, programming being effected by thermal links respectively connected to the respective transistors and which undergo a change in conductive state when subjected to a programming current of sufficient magnitude. The programming circuit includes a row driver having an FET gate which in response to a row address selection pulse turns on a bipolar transistor (Q1), the FET gate otherwise maintaining Q1 off. Transistor Q1 forms a Darlington pair with any of the transistors in the corresponding row of the array which are turned on. The transistors in respective columns of the array are connected in common by respective column conductors to respective transmission gates, each transmission gate including another Darlington bipolar pair driven by a CMOS inverter. The inverter opens the transmission gate in response to a strobe pulse which is concurrent with a column selection pulse from the column decoder, but otherwise maintains the transmission gate closed. A significant reduction in power consumption, and consequent heat dissipation, is achieved because the row drivers and transmission gates for non-selected rows and columns do not require quiescent operating current, and programming current for a selected transistor is supplied in a path comprising only bipolar Darlington pairs.