The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1991
Filed:
Dec. 02, 1988
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code. The device has a first circuit train including a series connection of plural stages of operation circuits for receiving input data, performing predetermined operations while the input data propagates through the operation circuits and providing output data; a second circuit train including a series connection of plural stages of error detection code correction circuits for receiving error detection code input corresponding to the input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in the first circuit train, and outputting an error detection code corresponding to the output data; and at least one error detection circuit for performing a comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train. Also, the semiconductor integrated circuit device of this invention comprises a logic circuit incorporating therein an error detection function by doubling the circuits which comprise a logic circuit using the error detection code, doubled operation circuits having the same function and inputted with the same signal, and a comparison circuit for mutually comparing the outputs of the doubled operation circuits.