The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1991
Filed:
Sep. 05, 1989
Mark D Bader, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A memory for performing read cycles and write cycles has memory cells located at intersections of word lines and complementary bit line pairs. A row decoder receives a row address and drives a word line in response. In the read cycle, a column decoder decodes a column address to couple selected bit line pairs to global data lines for subsequent output. In the write cycle, write global data lines receive input data signals and couple them to selected bit line pairs for storage in memory cells located at intersections of the selected bit line pairs and enabled word lines. After the write cycle, equalization of bit lines is achieved partly by bit line loads coupled to each bit line, and partly by write data line loads located in the column decoder. Because the write data line loads are coupled to the bit lines after column decoding has taken place, the write data line loads can be shared by several bit line pairs. Thus, layout space is saved due to the sharing, and transistors in the write data line load can be made larger to improve the speed of the bit line equalization.