The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 1991

Filed:

Dec. 16, 1988
Applicant:
Inventors:

Hidenori Inouchi, Fuchu, JP;

Haruo Yoda, Nishitama, JP;

Hiroshi Ouchi, Higashiyamato, JP;

Hiroshi Sakou, Shiki, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G06F / ;
U.S. Cl.
CPC ...
364200 ; 3642318 ; 364239 ; 3642396 ; 3642386 ; 3642283 ; 3642384 ; 364271 ; 3642712 ;
Abstract

A pipe-lined data processor system comprising a plurality of processors interconnected in the form of a pipe line, a plurality of memory apparatus connected to each of the processors through output data buses for supplying data to the processors or storing data from the processors, and a control board connected to the memory apparatus through input data buses for managing the operation sequences of the processors and the memory apparatus, wherein the plurality of memory apparatus comprise each a main memory for storing the data to be processed as predetermined by the processors or the data having been processed as predetermined by the processors, a buffer memory for temporarily storing the data, first control means for controlling the timing of input/output of the data between the main memory and the buffer memory, and second control means for controlling the timing of input/output of the data between the buffer memory and the input/output buses.


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