The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1991
Filed:
Mar. 27, 1989
Richard H Wyles, Cardiff, CA (US);
James L Gates, Vista, CA (US);
Steven D Gaalema, Encinitas, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A readout circuit for use with a focal plane array that employs a single transistor in each unit cell and a single capacitive feedback transimpedance amplifier to process the outputs of each column of detector elements of the array. The capacitive feedback transimpedance amplifiers extract the signals associated with the pixels along a particular row of the array. The present invention permits high performance readouts to be constructed with very little circuitry in the unit cells. Only a single minimum sized transistor switch is required in each unit cell to perform readout and reset functions for the array. In the disclosed embodiment, the readout circuit comprises an array of unit cells, each cell comprising a detector input circuit, a single transistor and a single charge storage capacitor. Row address circuits are coupled to the cells in each row of the array. A plurality of capacitive feedback transimpedance amplifiers are coupled to the cells in each column of the array. The amplifiers process charge derived from the detector elements and stored in the charge storage capacitor of each unit cell. Column multiplexing circuits multiplex the output signals provided by each of the amplifiers. Column address circuits are coupled to the column multiplexing circuits which couple output signals from each of the multiplexer circuits as the output from the readout circuit.