Structured scan path circuit for incorporating domino logic

Abstract

A design for a structured scan path circuit incorporating domino logic circuitry is provided. The scan path circuit allows the rapid evaluation of a predetermined logic function, while allowing the use of automatic test pattern generation programs. Each function input signal has its own latch, the equivalent to the master latch in a standard scan flip-flop. The domino function output also has a latch, the equivalent of the slave latch in the scan flip-flop. The use of the input latches eliminates the need to insure the stability of the function input signals during the evaluation of the domino logic function. Thus, the input latches eliminate the potential 'hazard' problems which can occur due to the instability of the input signals during evaluation of the domino logic function. A scan enable signal selectively enables and disables the function evaluation by the domino logic circuitry. Thus, the function evaluation may be disabled for a 'capture' interval, to allow the scan circuit to scan in a scan data value, and scan out the same scan data value, via the slave on the function output. The scan circuit also incorporates decoder circuitry to further increase the speed at which the scan path circuit evaluates the logic function.