The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 1991
Filed:
Aug. 02, 1989
Robert D Maher, III, Carrollton, TX (US);
Cyrix Corporation, Dallas, TX (US);
Abstract
An arithemtic circuit (10) which comprises an adder/rounder circuit (20) and a normalization estimation circuit (24) coupled in parallel to operand register (14, 19). A signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) performs a three-bit overlapping scan of the signed digit differene to determine a bit location which corresponds to the approximate bit position of the most significant non-zero bit in the result of the arithmetic process performed in adder/rounder circuit (20). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue. The number of leading zeroes is output to a barrel shifter (16) via an L-bus (30). The operands are simultaneously substracted in adder/rounder circuit (20) and the result is input into barrel shifter (16) via an M-bus (12). The result is then shifted in barrel shifter (16) according to the leading zero count input by leading zero counter (18). The shifted result is then input into a conditional shifter (18) which outputs the normalized result for subsequent rounding procedures and two's complement conversion.