Arithmetic circuit for calculating and accumulating absolute values of

Abstract

An arithmetic circuit for calculating and accumulating absolute values of differences between first and second numerical values having a predetermined bit length and represented by 2's compliment notation is provided by a first inverter for inverting the second numerical value to produce an inverted value; a first adder receiving the first numerical value and the inverted numerical value and generating a sum as a first addition result; and a selector receiving the first addition result from first adder and an inverted addition result from the first adder via a second inverter and outputting a selected value based on the sign of the first addition result. A correcting value generating circuit generates a correcting value based on the sign of the first addition result. A second adder receives the selected value, the correcting value and a delayed addition result and generates a sum as a second addition result, which is output to a first delay circuit. The first delay circuit delays the second addition result by a predetermined delay and outputs the delayed addition result as an operation result while providing the delayed addition result to the second adder. Additional delay circuits responsive to a clock signal can be operatively coupled between the selector and the second adder to match the speeds of the selector and the first delay circuit.