Fault powered, processor controlled circuit breaker trip system having

Abstract

A fault-powered, processor-based tripping system includes a solenoid for interrupting a current path in response to a trip signal generated by a processor. The processor analyzes current provided by a current sensor, by way of an interface circuit, to determine when the trip signal should be generated. A power supply provides a reference signal to the processor to indicate the amount of power it is capable of delivering to the solenoid. Before attempting to engage the solenoid, the processor checks the level of the reference signal to determine whether or not the power supply is at that time capable of supplying the solenoid with a sufficient amount of power to effect interruption of the current path thereby avoiding a power loss by inappropriate engagement of the solenoid. If the power level is sufficient to engage the solenoid, the processor generates the trip signal to interrupt the current path.