Wafer scale integrated circuit apparatus

Abstract

Wafer scale integrated circuit apparatus wherein a full wafer scale semiconductor integrated wafer is adhesively secured to an essentially flat heat conducting non-metallic base member with the wafer and base member having coefficients of thermal expansion approximately equal to one another. A cable adapter assembly connected to an edge of the base member secures one or more multiconductor flat cables in position such that the conductors thereof, by means of a clamping arrangement make positive pressure contacts with contact points connected to electronic circuitry of the semiconductor wafer. Another wafer may be placed on an opposed surface of the base member and a second cable adapter assembly may be utilized to secure another multiconductor flat cable for making interconnection between contact points of the wafer on one surface with contact points of the wafer on the opposed surface of the base member. The arrangement constitutes a wafer module and a plurality of such identical wafer modules may be stacked one upon the other and placed in a housing which has heat conducting side walls for heat dissipation purposes. A cable link assembly traverses the flat cables held in position by the first cable adapter assemblies of the wafer modules in order to serve for the inputting and outputting of electrical signals.