The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 1991

Filed:

Mar. 16, 1990
Applicant:
Inventors:

Adrian P Wise, Bristol, GB;

Richard M Forsyth, Bristol, GB;

Assignee:

Inmos Limited, Bristol, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
36523003 ; 365194 ; 365233 ; 365203 ; 365239 ;
Abstract

A line delay device comprises a memory having RAM cells in two blocks, each cell being connected to a pair of bit lines. Memory locations in one block are addressed sequentially and subject to a data transfer while an equate operation is effected on the bit lines of the other block. The operations are switched alternately between the two blocks. In each accessing cycle, a plurality of locations are addressed in selected rows of each block and the switching between each block is effected without addressing all locations in each row addressed so that the accessing cycle ends in a different block from the starting block and each row used has a plurality of addressed locations.


Find Patent Forward Citations

Wise, Adrian. (1991). Memory accessing (U.S. Patent No. 5036494). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5036494

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…