The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 1991

Filed:

Jul. 19, 1989
Applicant:
Inventors:

Yoshio Yasumoto, Nara, JP;

Sadashi Kageyama, Hirakata, JP;

Syuji Inoue, Neyagawa, JP;

Yoshio Abe, Ibaraki, JP;

Hideyo Uwabata, Neyagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N / ; H04N / ;
U.S. Cl.
CPC ...
358 12 ; 358 11 ; 358140 ; 358141 ;
Abstract

A signal processing apparatus in a television signal transmitting system includes: a first group of delay lines for obtaining a first series of parallel signals; a first group of coefficient multipliers for weighting the first series of signals; a first adder for adding outputs of the first group of coefficient multipliers; a second group of delay lines for obtaining a second series of parallel signals; a second group of coefficient multipliers for weighting the second series of signals; a second adder for adding outputs of the second group of coefficient multipliers and one of the first series of signals; and a transmitter for transmitting output signals from the first and second adders. A signal processing apparatus in a television signal receiving system includes: an input circuit for receiving first and second signals; a first group of delay lines for obtaining a first series of parallel signals; a first group of coefficient multipliers for weighting the first series of signals; a first adder for adding outputs of the first group of coefficient multipliers and the second signal; a second group of delay lines for obtaining a second series of parallel signals; a second group of coefficient multipliers for weighting the second series of signals; a coefficient multiplier for weighting one of the first series of signals; a second adder for adding outputs of the second group of coefficient multipliers and the coefficient multiplier; and a signal composer for composing the output signals from the first and second adders.


Find Patent Forward Citations

Loading…