Precise, high speed cmos track (sample)/hold circuits

Abstract

A precise, high speed CMOS track (sample)/hold circuit uses a first circuit leg including four Schottky barrier diodes configured to form a Wheatstone bridge, a second leg with a single n-channel MOS transistor, an essentially constant current source having MOS transistors, a capacitor for holding output signal, and reverse biasing circuitry having MOS transistors for selectively reverse biasing the four diodes. An analog input signal is applied to the cathode of the first diode and to the anode of the second diode. An output signal of the same magnitude and polarity as the input signal is generated at an output terminal (the cathode of the third diode and the anode of the fourth diode) of the circuit when current flows through the first circuit leg. When the current flowing through the first circuit leg is switched to the second circuit leg, the capacitor, which is connected to an output terminal of the circuitry, holds the generated output signal level and the reverse biasing circuitry reverse biases all of the diodes so as to isolate the capacitor from all other components of the circuit.