Method of manufacturing cmos eprom memory cells

Abstract

A method of manufacturing memory cells is described, wherein the great selectivity of polysilicon etching with respect to oxide is employed for the elimination of the self-aligned polysilicon mask for the definition of the floating gate of the EPROM cell. In fact, according to the invention, the mask for the formation of the source and drain regions of one of the CMOS transistors is used for the removal of the oxide separating the two layers of polysilicon on the active region defining a memory cell, and the mask for the formation of the source and drain regions of the other CMOS transistor is employed for the removal of the lower layer of polysilicon around the floating gate of the memory cell, wherein the silicon portions which are not to be removed are covered by oxide.