High speed ttl buffer circuit and line driver

Abstract

A non-inverting TTL buffer circuit provides an input for receiving data signals at high and low potential levels and an output for transmitting data signals in phase with the input. The base node of an emitter follower transistor element is coupled to a collector node of the input transistor circuit in an inverting coupling. The emitter node is coupled to a base node of the phase splitter transistor element for sourcing base driven current to the phase splitter transistor element in response to data signals at the input. The emitter follower provides transient 'overdrive' for fast turn on of the phase splitter. A first clamp circuit between the base node of the emitter follower transistor element and the low potential power rail clamps the base node at a low potential level when the emitter follower transistor element is relatively non-conducting and establishes the input threshold voltage level. A second clamp circuit coupled to the base node of the emitter follower transistor element clamps the base node at a high potential level for limiting base drive current to the phase splitter transistor element from the emitter follower transistor element. The second clamp circuit limits saturation of the phase splitter transistor element and improves switching speed. The second clamp circuit is preferably coupled between the base node of the emitter follower transistor element and a collector node of the phase splitter transistor element and includes a 'programmable' resistor voltage drop component for limiting operation of the phase splitter transistor element to the desired operating region.