Dual mode memory read cycle time reduction system which generates read

Abstract

An apparatus for reading data from a memory in a computer system includes: an address register for holding an address to be supplied to the memory, a read data register for holding data read out from the memory and a device for generating a gated clock signal from a free-running clock signal having a predetermined constant period of time. The gated clock signal is free-running with the predetermined constant period of time in a normal clock mode but is generated by a single pulse with an interval longer than the period of the free-running clock signal in a single clock mode. A device, having serially connected plural registers for shifting a trigger signal in accordance with the free-running clock signal generates a read data clock signal. The trigger signal has a same timing synchronized with a specific phase of the gated clock signal at which a phase of the address register is switched to hold a new address to be supplied to the memory. The shifted trigger signal is fed to the read data register for hodling the data read out from the memory.