Data bank priority system

Abstract

A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.