Information processing system with instruction address saving function

Abstract

A level machine information system is provided with an instruction register for storing an address of an instruction read out from an instruction memory, an instruction decoder for producing control signals complying with the instruction read out, a calculator for producing a new address of an instruction to be executed next on the basis of the address outputted from the instruction register, an instruction length code supplied from the decoder as the control signals, a plurality of first registers for saying the address outputted from the instruction register, a plurality of second registers for saving the new address, a controller and a selector for supplying the instruction register with the new address, the saved new address and fixed addresses each indicating the head of interruption programs in the instruction memory. The first and second registers correspond to all but the highest interruption priority level. Upon an acknowledged interruption request, the controller controls the first and second registers and selector to save the new address of the calculator and the old address of the instruction register in one of the first and second registers corresponding to the priority levels of an interrupted process, respectively. One of the fixed addresses corresponding to a process to be executed for the interruption request is transferred in the instruction register. If necessary, the contents of the first and second registers are referenced by the process to detect the reasons for the interruption.