The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 1991

Filed:

May. 15, 1990
Applicant:
Inventors:

Shinichi Takagi, Tokyo, JP;

Kenji Natori, Kawasaki, JP;

Junji Koga, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; G11C / ;
U.S. Cl.
CPC ...
357 41 ; 357 12 ; 357-4 ; 357 51 ; 365175 ; 365176 ; 365182 ;
Abstract

Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.


Find Patent Forward Citations

Loading…