The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 1991
Filed:
May. 29, 1990
Yoshinori Okumura, Hyogo, JP;
Takayuki Matsukawa, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A semiconductor device comprises a P type semiconductor substrate (1) with a trench (12) formed on a main surface thereof. An N type drain region (15a) is formed at the bottom surface portion of the trench (12). An insulating layer (19c) is formed on the surface of the substrate (1) including a sidewall and the bottom surface of the trench (12), the layer having a hole (20b) whose bottom surface being at least the surface of the drain region (15a). A conductive layer (18) is formed on the insulating layer (19c) which is contact with the drain region (15a) at the bottom surface of the trench (12) through the hole (20b). The conductive layer (18) consititues a drain electrode. A gate (13) is interposed between the conductive layer (18) and the sidewall of the trench (12), formed along the sidewall of the trench (12) and insulated by the insulating layer (19c). An N type source region (15b) is formed on the surface of the substrate (1) including a portion of the sidewall of the trench (12). The drain electrode, the source electrode and the gate (13) constitute a MOS type field effect transistor (T2). At least a portion of a channel region is formed on the sidewall portion of the trench (12) between the drain region (15a) and the source region (15b). A capacitor (C2) is formed on the surface of the substrate (1) to be connected to the field effect transistor (T2).