Decoder for added asynchronous bit sequences

Abstract

A composite signal is formed by simultaneously transmitting multiple asynchronous data bit sequences, that are coded with respective spreading codes, in a single channel; and a circuit is provided which decodes any bit b(x) in that composite signal. This circuit includes a set of filters which are matched to all of the spreading codes and which obtain (a) a matched filter output signal y(x) for the x-th data bit b(x) and (b) matched filter output signals y(x+1) thru y(x+k-1) for the k-1 data bits that immediately follow data bit b(x); K is the number of bit sequences in the composite signal. An arithmetic unit combines the matched filter output signals via the expression: ##EQU1## where H(x,x.+-.i) is the cross correlation of the spreading codes for data bits b(x) and b(x.+-.i) over the time period that those data bits overlap (and thus add) in the composite signal, and ESTb(x-i) is an estimate of data bit b(x-i) which precedes bit b(x). An output unit decodes the data bit b(x) as a '1' if the above expression is positive, and as a '0' if the above expression is negative. In one embodiment, ESTb(x-i) is the SIGN of a matched filter output y(x-i) for data bit b(x-i). In another embodiment, ESTb(x-i) is the result from the output unit which decoded data bit b(x-i).