Logic analyzer with double triggering action

Abstract

A logic analyzer for plural input channels generates trigger signals for first and second triggering modes selected by a multiplexer. In the first mode, a channel selector produces a detection signal in the form of a pulse when the plural input channels simultaneously have logic states matching a reference combination input to the channel selector. In the second mode, the channel selector produces a detection signal in the form of a pulse corresponding to the logic state of a channel selected by a channel selection signal input to the channel selector. The first mode triggering signal exhibits a digital transition when the pulse endures at least as long as a target time period determined by a target count times the interval between clock pulses while the second mode trigger signal exhibits a digital transition when the pulse terminates before enduring for the target time period.