The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 1991

Filed:

Sep. 14, 1989
Applicant:
Inventor:

Hiroshi Momose, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 43 ; 357 46 ; 357 34 ; 357 234 ;
Abstract

A semiconductor device according to the present invention comprises a P-channel MOSFET having a gate, a source, and a drain, and a bipolar transistor having a collector, a base, and an emitter. The semiconductor device also includes an N.sup.- -type collector diffusion layer formed in an epitaxial layer on a P-type semiconductor substrate and adjacent to an N.sup.+ -type buried collector diffusion layer, and an N.sup.+ -type electrode lead-out region formed in contact with the N.sup.+ -type buried collector diffusion layer having an impurity concentration higher than the N.sup.- -type collector layer. A gate electrode section constituted by a gate oxide film and a gate electrode is formed on the N.sup.- -type collector layer and the N.sup.+ -type electrode lead-out region, and an P-type impurity is ion-implanted into the source region of the P-channel MOSFET and and an N-type impurity is doped into the emitter region of the bipolar transistor, with the gate electrode section being used as a mask. Furthermore, a P-type impurity is ion-implanted into a common area of the drain region of the P-channel MOSFET and the base region of the bipolar transistor and is diffused into the common area to a preset depth. Thus, the semiconductor device of bipolar-CMOS structure having a drain and base as the common area can be obtained.


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