Quasicomplementary mesfet logic circuit with increased noise imunity

Abstract

Disclosed is a logic circuit performing a quasi-complementary operation. This logic circuit includes a load transistor having a drain connected to a first power supply, a drive transistor having a source connected to a second power supply, a level shift diode connected between a source of the load transistor and a drain of the drive transistor, a resistor connected between a gate of the load transistor and the first power supply, an input portion for applying a signal for complementarily turning on the load transistor and drive transistor in response to an input signal, and a resistor connected between a gate of the drive transistor and the second power supply. Therefore, a gate potential of the load transistor is set to a potential which is always higher than a drain voltage, so as to prevent an output high level from being lowered and expand a logic voltage swing. Further, there is disclosed a logic circuit in which a plurality of quasi-complementary logic circuits are coupled by a wired logic. This circuit configuration enables the number of gate stages to be reduced in case where the plurality of logic circuits are coupled.