The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 1991

Filed:

Jun. 25, 1990
Applicant:
Inventors:

Edward Li, Roselle, IL (US);

John E Herrmann, Mundelein, IL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01H / ;
U.S. Cl.
CPC ...
307135 ; 307115 ; 323908 ; 361 58 ;
Abstract

A DC power switch (10) for a capacitive load (11) has a main transistor (Q1) in series with the load between positive and negative DC bus terminals (B.sup.+, B.sup.-). A secondary transistor (Q2) and a resistor (R.sub.1) are connected in series and this series connection is connected in parallel to the main transistor (Q1). A control circuit (20; 50) is connected to the main and secondary transistors (Q1, Q2) and controls them. In response to an enable signal (26), the secondary transistor (Q2) is initially turned on such that it and the resistor provide the initial charging current for the capacitor load (11) and subsequently the secondary transistor is turned off and the main transistor is turned on such that it provides the subsequent current required by the load. This configuration minimizes the power dissipation ratings required for the transistors while balancing this requirement with the relative rapid providing of charging current for the capacitive load. Fault detection circuitry (30-33) makes sure both the main and secondary transistors are off and interrupts the supply of DC power to the load (11) in the event of a detected fault.


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