The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 1991

Filed:

Apr. 02, 1990
Applicant:
Inventors:

Tadakuni Narabu, Kanagawa, JP;

Masaharu Hamasaki, Kanagawa, JP;

Tetsuya Iizuka, Kanagawa, JP;

Assignee:

Sony Corporaiton, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; H01L / ; H03F / ; H03F / ;
U.S. Cl.
CPC ...
377 60 ; 357 24 ; 330277 ; 330292 ;
Abstract

An output circuit for CCD imager devices or CCD delay devices is disclosed in which a depletion type second MIS transistor is connected to the drain side of a first MIS transistor constituting a source follower adapted for converting transferred signal signals into an electrical voltage, and an output voltage is supplied to the gate of the second MIS transistor. This depletion type second MIS transistor causes the drain potential of the first MIS transistor to be changed in phase with the input electrical charges to reduce the gate-to-drain capacitance of the first MIS transistor to improve the charge-to-voltage conversion gain.


Find Patent Forward Citations

Narabu, Tadakuni. (1991). Output circuit having high charge to voltage conversion gain (U.S. Patent No. 5029190). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5029190

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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