The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 1991

Filed:

Aug. 29, 1989
Applicant:
Inventor:

Manabu Ando, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
3652335 ; 365203 ; 36518908 ; 36523003 ;
Abstract

An asynchronous type static memory device in which a plurality of pairs of bit lines are equalized upon change of address signals at a high speed is disclosed. The memory device comprises a plurality of memory blocks having a plurality of pairs of bit lines and a plurality of equalizing circuits provided for the plurality of pairs of bit lines, a plurality of address terminals receiving address signals, and an address transistion detecting circuit having a plurality of detection units, each of the detection units being coupled to one of the address terminals and generating a detecting signal when the signal at the associated address terminal coupled thereto is changed, a first logic section for generating a first number of intermediate logic signals for performing logical sum with respect to outputs of the detection units, the first number being smaller than the number of the detection units, and a plurality of second logic sections provided for the plurality of memory blocks respectively, each of the second logic sections operatively generating a control signal for enabling the equalizing circuits associated therewith as a result of performing a logical sum of the intermediate logic signals.


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