Semiconductor memory device with tandem sense amplifier units

Abstract

A semiconductor memory device is used for storing data bits in memory cells thereof, and the data bits are read out from the memory cells in the form of small differences in voltage level on bit line pairs coupled to the memory cells, wherein gate transistors are inserted between each of the bit line pairs and a pair of sense nodes, and in which the bit line pair and the sense node pair are respectively associated with first and second sense amplifier circuits for rapidly increasing the small difference in voltage level, because the electric charges accumulated in the bit line pair are shared by the first and second sense amplifier circuits.