The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 1991
Filed:
Aug. 04, 1988
Surendar S Magar, Colorado Springs, CO (US);
Gerry C Lui Kuo, Colorado Springs, CO (US);
Raul A Aguilar, Colorado Springs, CO (US);
Michael E Fleming, Colorado Springs, CO (US);
Array Microsystems, Inc., Colorado Springs, CO (US);
Abstract
A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, the application of members of a signal array to be processed and the removal of the members of a processed signal array from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and the associated memory units. The control apparatus permits the digital signal processing device and associated memory units to operate in a normal mode where a predetermined processing operation is performed on the members of a signal array, a recursive mode where a series of operations are performed on a signal array by a single digital signal processing unit, and a sequential mode where a series of processing operations are performed on a signal array using a by plurality of digital signal processing units coupled in a series arrangement. The control apparatus has provision for automatic accommodation of predetermined latency in the signal member path, resulting from pipelined computation and from pipelined memory accesses, as well as accommodating preselected signal array sizes and preselected signal array overlap.