Apparatus and method for providing a settling time cycle for a system

Abstract

In a data processing system in which a plurality of data processing units or subsystems exchange logic signal groups by means of a system bus, apparatus is provided to allow sufficient time to permit transients on the system bus to decay, thereby increasing the integrity of the data. When the logic signal groups are applied to the system bus via conducting and nonconducting transistors, the presence of a logic signal on the system bus immediately prior to the application of a set of logic signals from a different data processing unit can delay the on-set of conduction of the most recently activated transistors, thereby resulting in transients of long duration. To accommodate these long transient conditions, the application of the new set of logic signals can be delayed until the transients on the system bus have been attenuated. Apparatus is disclosed for prohibiting access to the system bus by any subsystem during the system clock cycle following a subsystem access or by preventing access to the system bus by subsystems determined by the subsystem having access during the prior system clock cycle.