Process for fabricating radiation hard high voltage devices

Abstract

A radiation hard, high voltage integrated circuit device fabrication process. A silicon substrate is implanted with ions that form a buried layer and an epitaxial layer of silicon is grown thereover. The structure is heated to form adjacent N- and P-channel regions. Channel stops are then formed surrounding the respective channel regions. After forming the channel stops, the substrate is masked and predefined dopant ions are implanted into the source and drain regions of the respective wells in the substrate. The distribution of the dopant ions therein are adjusted to have a predetermined doping profile that defines a graded junction. Then the substrate is heated to a relatively high temperature to provide a high temperature drive cycle that forms a desired graded junction profile. A field oxide layer is then deposited on the substrate, and it is masked and etched to define active areas. A gate oxide layer is grown on the substrate above the active areas, and polysilicon gates are formed thereon. Finally, dopant ions are implanted into source and drain regions using the polysilicon gates and field oxide layer as a mask. This forms the completed semiconductor devices. The devices fabricated using this process have N.sup.+ (source and drain regions) to P-well and complementary P.sup.+ to N-well junction breakdown voltages in the 10-12 volt range, and the radiation performance of the devices is not degraded.