Image-processing integrated circuit device

Abstract

An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.