Logic circuit and design method for improved testability

Abstract

A method for designing integrated circuits for improved testability. A main logic function operable in initialization and test modes is defined in terms of component logic macros. Testability circuitry for generating CLEAR, CLEAR0 and CLEAR1 testability signals is also defined. The CLEAR signals have the first logic state during system operation in the initialization mode, and first and second logic states equal amounts of time during the test mode. The CLEAR0 signals have the first logic state during the initialization mode, and have the second logic state most of the time and the first logic state the remainder of the time during the test mode. The CLEAR1 signals have the first logic state during the initialization mode, and have the first logic state most of the time and the second logic state the remainder of the time during the test mode. First-type macros, such as multiplexers having Select or other inputs requiring CLEAR signals during the test mode, are identified. Second-type macros such as flip flops having clear, set or other inputs requiring CLEAR0 signals during the test mode are identified. Third-type macros such as flip flops having Enable or other inputs requiring CLEAR1 signals during the test mode are identified. Interconnections between the identified first, second and third-type macros and associated CLEAR, CLEAR0 and CLEAR1 signals are defined. Both logic and timing simulations and testability analysis on the integrated circuit can then be performed before the main logic function is redefined.