Two level multiplexer circuit shifter apparatus

Abstract

A shifter includes first and second levels or stages of multiplexer circuits. The inputs of the first stage multiplexer circuits are connected to receive in parallel, a plurality of sets of input operand signals which can be shifted in either direction over a wide range of bit positions. The outputs of these multiplexer circuits are selectively connected to the inputs of a smaller number of second stage multiplexer circuits. Different combinations of the plurality of sets of input operand signals are applied to the different inputs of each first stage multiplexer circuit and different combinations of first level multiplexer outputs are applied to the inputs of each second stage multiplexer circuit. Shift control circuits condition the first and second stage multiplexer circuits to select sets of outputs corresponding to different operand shifts, whose logical sum produces an operand shifted by the specified amount.