Dual polarity floating gate mos analog memory device

Abstract

A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.