Phase detector for phase-locked loop clock recovery system

Abstract

A phase-detector circuit for a phase-locked loop clock recovery system detects the phase difference between an information signal and a clock signal and produces a phase error signal representative of the phase difference. The phase detector includes, in one embodiment, five latches, serially interconnected, with the first latch receiving the information signal and each subsequent latch receiving the data output of the previous latch. The latches are enabled, in an alternating pattern, by the high-level and low-level portions of the clock signal. A first exclusive-OR (XOR) gate receives a delayed information signal and the data output of the second latch. A second XOR gate receives the data output of the second latch and the data output of the third latch. A third XOR gate receives the data output of the third latch and the data output of the fourth latch. A fourth XOR gate receives the data output of the fourth latch and the data output of the fifth latch. A control element, responsive to the outputs of the first, second, third and fourth XOR gates, controls the voltage across a capacitor, which has at least one electrode serving as an output terminal for producing the phase error signal. The phase-locked loop clock recovery system provides zero static phase offset and minimal phase jitter in response to data density variations in the information signal.