The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 1991

Filed:

Feb. 16, 1990
Applicant:
Inventors:

Yukihiro Saeki, Yokohama, JP;

Yasoji Suzuki, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307465 ; 307469 ; 307473 ;
Abstract

A programmable logic circuit for deriving a logic output of first and second signals includes a 2-input logic gate for deriving a logic output of two signals. The 2-input logic gate is constituted by connecting two 3-state circuits in a wired OR configuration. One of the 3-state circuits includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives an inverted signal of the second signal, and the data output terminal is set to one of three states of '1', '0', and the high impedance. Likewise, the other 3-state circuit includes a data input terminal, output control input terminal, and data output terminal, the output control input terminal receives the second signal, and the data output terminal is set to one of three states of '1', '0', and the high impedance. Each of the data input terminals of the 3-state circuits is supplied with a desired one of the first signal, an inverted signal of the first signal, a '0' level signal, and a '1' level signal in a programmable fashion. Various logic gates can be realized by programming the supplying states of the four signals.


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