Ffl/qfl fet logic circuits

Abstract

An FFL/QFL family of logic gates is disclosed, preferably implemented with GaAs MESFET devices and providing enhanced speed-power characteristics. Although a number of gate configurations are disclosed, a NOR gate 26 constructed in accordance with this invention includes a pair of normally OFF input transistors Q1 and Q7, which receive inputs A and B. Current sources Q2 and Q3 couple the transistors to the supply voltage V.sub.DD and ground, respectively. A control transistor Q6 is also coupled to the input and source transistors. An output section 30 responds to the combined operation of transistors Q1, Q2, Q3, Q6, and Q7 to produce an output C in accordance with conventional NOR logic. More particularly, upon application of a high logic input A or B to transistors Q1 and/or Q7, transistors Q1 and/or Q7 and Q6 turn ON and the output C is at a logic low level. If both inputs A and B are low, however, transistors Q1, Q6, and Q7 remain OFF, and the output C is at a high logic level. Use of the control transistor Q6 allows smaller input transistors Q1 and Q7 and current source Q3 to be used, increasing the integration level and gate speed via decreased capacitance.