The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 1991

Filed:

Sep. 25, 1989
Applicant:
Inventors:

Masaru Masuyama, Sagamihara, JP;

Yoshihiro Takemae, Tokyo, JP;

Tetsuhiko Endoh, Inagi, JP;

Hirosuke Komyoji, Minokamo, JP;

Ryuji Tanaka, Kawasaki, JP;

Katsuhiko Itakura, Minokamo, JP;

Assignees:

Fujitsu Limited, Kawasaki, JP;

Fujitsu Vlsi Limited, Kasugai, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365 52 ; 365 64 ; 3652385 ; 36523006 ; 235492 ;
Abstract

A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card. The memory card comprises a data input/output terminal, a memory part having a data bus with a bit width of at least n bits for coupling to the data bus of the card write and/or read apparatus via the data input/output terminal, an address input terminal for receiving an address signal, a first input terminal for receiving a first chip select signal which selects a first byte, a second input terminal for receiving a second chip select signal which selects a second byte, and a decoder circuit for determining a bit width of the data bus of the memory part to be used for data communication between the card write and/or read apparatus to one of n bits and n/N bits based on the first and second chip select signals and one or a plurality of arbitrary bits of the address signal by supplying control signals to the memory part, where n, N and n/N are positive integers.


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