The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 1991

Filed:

Jun. 15, 1989
Applicant:
Inventor:

Gensuke Goto, Ebina, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364786 ;
Abstract

A carry propagation circuit of a parallel-type full adder having a plurality of bits. The carry propagation circuit includes: a control unit for controlling a carry propagation; a main path including a plurality of transfer circuits serially connected and provided for each of the plurality of bits, each transferring a carry signal from a lower bit to a higher bit when it is brought to an ON state by the control unit; and at least one bypath arranged to bypass a predetermined number of the transfer circuits and brought to an enable state or a disable state by the control unit. When the control unit brings the bypath to the enable state, it brings to the OFF state a transfer circuit provided immediately in the lower bit side of the main path seen from a terminated point of the bypath and thus propagates only a carry signal propagated via the bypath to the higher bit side. This contributes to reducing the propagation delay time required for a carry operation to the minimum and thus realizing a high speed operational processing.


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