The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 1991

Filed:

Sep. 06, 1989
Applicant:
Inventors:

Tadashi Kiriseko, Kanagawa, JP;

Hiromichi Tani, Kawasaki, JP;

Noriko Soma, Yokohama, JP;

Nobuhisa Shigemi, Kawasaki, JP;

Takayuki Toyoda, Yokkaichi, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B65H / ;
U.S. Cl.
CPC ...
414222 ; 414273 ; 414286 ; 901-7 ;
Abstract

A continuous semiconductor substrate processing system is operated by a system control structure in accordance with a predetermined processing program. A wafer conveying mechanism conveys wafers to and from each of plural process stations, each of which performs a corresponding process step on semiconductor wafers, to and from a stocker and to and from an inspection unit. Carriers, movable by manual or mechanical structure other than the wafer conveying mechanism, provide for alternative conveying of wafers to and from each of the process stations, the stocker and the inspection station. The system control structure monitors and selectively controls each of the wafer conveying mechanism, the process stations and the stocker and issues instructions for movement of the carriers and monitors the positioning of carriers for selective control of the transfer of wafers and the priority sequence of processing of wafers, to maintain continuous performance of plural process steps on plural lots of semiconductor wafers.


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