The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 1991

Filed:

Dec. 02, 1988
Applicant:
Inventor:

Brian K Herbert, Colorado Springs, CO (US);

Assignee:

NCR Corporation, Dayton, OH (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
36518908 ; 36518905 ; 365207 ; 307445 ;
Abstract

A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.

Published as:
GB8927204D0; GB2225657A; JPH02214090A; US5023838A; GB2225657B; JP2897886B2;

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