The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 1991

Filed:

Mar. 15, 1989
Applicant:
Inventors:

Adriano Mattera, Novara, IT;

Roberto Fornari, Parma, IT;

Renato Magnanini, Reggio Emilia, IT;

Carolo Paorici, Parma, IT;

Lucio Zanotti, Via S. Pellico, IT;

Giovanni Zuccalli, Parma, IT;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364480 ; 328 11 ; 219497 ;
Abstract

An interface circuit to the output of a programmable voltage ramp generator for decreasing the minimum voltage step of such a generator having two voltage channels and a minimum voltage step greater than 1 millivolt. The interface circuit receives an input from each of the two voltage channels (V.sub.2, V.sub.3), along with an inserted voltage (V.sub.1). The circuit includes a summing amplifier for (i) compressing the minimum voltage step from one voltage channel (V.sub.2) by a factor equal to or greater than such minimum voltage step, (ii) adding the voltage from the other channel (V.sub.3) to the compressed voltage, and (iii) subtracting the inserted voltage (V.sub.1) (or adding an inserted voltage which is negative). The inserted voltage (V.sub.1) is equal in magnitude to the maximum output value from the voltage channel that has the voltage compressed (V.sub.2). The output of the summing amplifier (V.sub.out) may be represented by:


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