The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 1991
Filed:
Mar. 13, 1990
Gerard Boudon, Mennecy, FR;
Pierre Mollier, Boissise Le Roi, FR;
Seiki Ogura, Hopewell Junction, NY (US);
Dominique Omet, Evry, FR;
Pascal Tannhof, Perthes, FR;
Franck Wallart, Cesson, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to fast complementary emitter follower drivers/buffers to be used in either a CMOS or pure complementary bipolar environment. The output driver (22) comprises top NPN and bottom PNP output transistors (T1, T2) with a common output node (N) connected therebetween. A terminal (15) is connected to the said output node (N) where the output signal (VOUT) is available. The pair of bipolar output transistors is biased between the first and second supply voltages (VH, GND). The output driver is provided with a voltage translator circuit (S) connected between the base nodes (B1, B2) of the output transistors (T1, T2). Logic signals (IN1, IN2), supplied by a preceding driving circuit (21), are applied to said base nodes. According to the invention, the voltage translator circuit (S) comprises two diodes (D1, D2) connected in series, preferably implemented with a main bipolar transistor having a junction shorted by a diode connected transistor to form a Darlington-like configuration. As a result, the voltage shift VS between the base nodes is selected to have the said output transistors operating at an operating point which ensures minimum delay and power consumption. In a typical bipolar technology, VS is made to be approximately equal to 1.5V. Additional features comprise the connection of a capacitor (C) between the base nodes and resistances (R1, R2) to the base nodes. The preceding driving circuit may be a CMOS logic gate or an ECL logic circuit.