The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1991

Filed:

Sep. 26, 1988
Applicant:
Inventors:

Yasuo Masaki, Osaka, JP;

Kimitoshi Hori, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K / ;
U.S. Cl.
CPC ...
382 49 ; 382 50 ; 358448 ;
Abstract

Each of the processing circuits connected to an image data bus is adapted such that a delay of n transfer clocks (n is a positive integer) or an integer multiple thereof is generated between the input and output data. Therefore, the delay time of the whole processing circuit becomes an integer multiple of a fixed time period, no matter what pipeline structure is adopted to connect the processing circuits. An address counter connected to the image memory through an address bus delays one read address by a plurality of cascade connected delay circuits and outputs the same as write address with the output of respective delay circuit switched successively, so that it seemingly operates in the same manner as in the case where there are a number of write address counters.


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