The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1991

Filed:

Jan. 11, 1988
Applicant:
Inventors:

Jy-Der Tai, Plano, TX (US);

Edison Chiu, Richardson, TX (US);

Quang-Dieu An, Dallas, TX (US);

Te-Chuan Hsu, Arlington, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G11C / ;
U.S. Cl.
CPC ...
364900 ; 364960 ; 3649602 ; 3649604 ; 3649606 ; 3649654 ; 364971 ; 365220 ;
Abstract

A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value. A gate circuit (111, 117, 139) is coupled to the latch (132), a flag signal output, the up/down signal source (11) and the clock signal source (13) and is operable to generate the flag signal in response to the stored decoded boundary value and the predetermined states of the up/down signal and the clock signal.


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