The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 1991

Filed:

Oct. 30, 1989
Applicant:
Inventors:

John R Pfiester, Austin, TX (US);

Richard W Mauntel, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; G11C / ;
U.S. Cl.
CPC ...
357 235 ; 357 59 ; 357 13 ; 357 71 ; 357 15 ; 365175 ;
Abstract

A compact SRAM cell and method for its fabrication are disclosed. The small size of the SRAM cell is achieved by fabricating a diode load immediately above the gate electrode of each of the cross coupled transistors of the cell. In accordance with one embodiment, the gate electrode and diode structure include, in sequence, an N-type doped polycrystalline silicon layer, an electrically conductive diffusion barrier layer, a P-type doped polycrystalline silicon layer and an N-type doped polycrystalline layer.


Find Patent Forward Citations

Pfiester, John. (1991). Compact sram cell with polycrystalline silicon diode load (U.S. Patent No. 5021849). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5021849

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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